In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pEETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2× higher than on a (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for NFET devices since that crystal orientation favors electron mobility.
Co-pending and co-assigned U.S. patent application Ser. No. 10/250,241, filed Jun. 17, 2003, provides an approach to fabricate CMOS devices on hybrid orientations wherein the pFETs are formed on a (110) surface orientation and nFETs are formed on a (100) surface orientation. Because hole mobility is greater than 150% higher on a (110) orientation than on a (100) orientation, the drive current of pFETs is greatly enhanced from conventional CMOS technology. However, this prior art approach puts one type of device on a silicon-on-insulator (SOI) and the other type of device on bulk (epitaxial layer) depending on the surface orientation of the SOI and the handle wafer. For example, with a (100) SOI and a (110) handle wafer, nFETs will be SOI devices and pFETs will be bulk-like devices. With a (110) SOI and a (100) handle wafer, nFETs will be bulk-like devices and pFETs will be SOI devices.
In general, bulk-like devices have larger junction capacitance than SOI devices and will affect circuit performance under AC conditions. Techniques are known which are capable of fabricating both types of devices on SOI, however the processing steps involved in these prior art techniques are very complicated.
In view of the above, there is a need to reduce the junction capacitance for the bulk-like device in the hybrid orientation structure using a simple process.